A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology

V
VLSID
2007
20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07)
Abstract - A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology

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	Similar Articles Articles by Rajiv V. Joshi Articles by Keunwoo Kim Articles by Richard Q. Williams Articles by Edward J. Nowak Articles by Ching-Te Chuang

20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07)

Bangalore, India

January 06-January 10

ISBN: 0-7695-2762-0

	ASCII Text	x
	Rajiv V. Joshi, Keunwoo Kim, Richard Q. Williams, Edward J. Nowak, Ching-Te Chuang, "A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology," VLSI Design, International Conference on, pp. 665-672, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007.

	BibTex	x
	@article{ 10.1109/VLSID.2007.182, author = {Rajiv V. Joshi and Keunwoo Kim and Richard Q. Williams and Edward J. Nowak and Ching-Te Chuang}, title = {A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2007}, issn = {1063-9667}, pages = {665-672}, doi = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2007.182}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology SN - 1063-9667 SP665 EP672 A1 - Rajiv V. Joshi, A1 - Keunwoo Kim, A1 - Richard Q. Williams, A1 - Edward J. Nowak, A1 - Ching-Te Chuang, PY - 2007 KW - null VL - 0 JA - VLSI Design, International Conference on ER -

Rajiv V. Joshi, IBM T. J. Watson Research Center, Yorktown Heights, NY

Keunwoo Kim, IBM T. J. Watson Research Center, Yorktown Heights, NY

Richard Q. Williams, IBM Technology Group, Essex Junction, VT 05452, U. S. A

Edward J. Nowak, IBM Technology Group, Essex Junction, VT 05452, U. S. A

Ching-Te Chuang, IBM T. J. Watson Research Center, Yorktown Heights, NY

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VLSID.2007.182

This paper describes back-gate biasing scheme using independent-gate controlled asymmetrical (n+/p+ polysilicon gates) FinFETs devices and its applications to 6-T and 8-T SRAM. Row-based above-VDD/below- GND bias is applied to the back-gates of the access and pull-down cell nFETs to enhance the Read/Write performance, reduce standby leakage, and mitigate process (VT) variability. The application of the technique to stacked Read transistors in 8-T SRAM is also discussed.

Citation:

Rajiv V. Joshi, Keunwoo Kim, Richard Q. Williams, Edward J. Nowak, Ching-Te Chuang, "A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology," vlsid, pp.665-672, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007

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