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20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07)
A Novel CMOS Full Adder
Bangalore, India
January 06-January 10
ISBN: 0-7695-2762-0
Keivan Navi, Shahid Beheshti University
Omid Kavehie, Shahid Beheshti University
Mahnoush Rouholamini, Research and Science Center of Hesarak Punak, Tehran, Iran
Amir Sahafi, Research and Science Center of Hesarak Punak, Tehran, Iran
Shima Mehrabi, Research and Science Center of Hesarak Punak, Tehran, Iran
This paper proposes a high-speed adder cell using a new design style called "bridge". The bridge design style offers more regularity and higher density than conventional CMOS design style, by using some transistors, named bridge transistors. Results show 4.4% (@ Vdd=3 volt) to 34.1% (@ Vdd=1 volt) improvement in speed over conventional CMOS adder. HSPICE is the circuit simulator used, and the technology being used for simulations is BSIM3v3 0.18?m technology.
Citation:
Keivan Navi, Omid Kavehie, Mahnoush Rouholamini, Amir Sahafi, Shima Mehrabi, "A Novel CMOS Full Adder," vlsid, pp.303-307, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007
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