This course will address advanced packaging and assembly technologies. Demands for increased miniaturization and performance of electronic systems have driven traditional IC packaging technologies to higher levels of sophistication and miniaturization.

The different styles of IC packages and their evolution will be discussed, from through-hole to surface mount, from leaded to leadless packages and from 2D to 3D packaging. Novel technology trends will be discussed, in particular wafer level packaging and 3D packaging technologies.

The ultimate miniaturised package has a size equal to the die size. Such packages may be fabricated at the wafer level, before die singulation. This not only results in the smallest possible packages, but also enables cost reduction. All die on a wafer are simultaneously packaged, in contrast to the sequential traditional package flows.

Further miniaturization and performance enhancement of electronic systems will more and more require the use of 3D interconnection schemes. Key technologies for realizing true 3D interconnect schemes are the realization of vertical connections, either through the Si-die or through the multilayer interconnect with embedded die.

Different applications require different complexities of 3D-interconnectivity. Therefore, different technologies may be used. These can be categorized as a more traditional packaging approach, a wafer-level-packaging, WLP (?above? passivation), approach and a foundry level (?below? passivation) approach. The trends for these different 3D-flavours will be discussed in more detail.