Power has become one of the most important paradigms of design convergence for future microprocessor and ASIC/SOC designs. In this tutorial we present the importance of low power microprocessor/SOC design from the high level microarchitectural, RTL, gate level to transistor level design. We cover the conflicting goals of performance vs low power, routinely faced by designers today. Embedded microprocessor/SOC designs are particularly dictated by standby and max/thermal design power and battery life constraints and not performance/frequency alone. Designing with the power envelope is a standard challenge even for the high end server platforms. Performance/watt or MIPS/watt is the design metric of today that we focus on.

We cover the main components of leakage power and how does the transistor design determines whether the extreme stringent battery life requirements determined by standby and average power are met. A short discussion of different process variants for various types of applications will also be discussed followed by an introduction of shadow latches and state retention techniques used by microprocessors and DSPs of today. Tradeoff between amount of state retained and the exit latency of the processor from deep sleep/standby states will be discussed.