20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07) A New Pseudo-Boolean Satisfiability based approach to Power Mode Schedulability Analysis Bangalore, India January 06-January 10 ISBN: 0-7695-2762-0
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VLSID.2007.16
It is important to know for a collection of tasks running in hand-held devices, if there is any way to schedule power modes to them which will maintain every temporal and power constraints. The peak power that the battery in the system can deliver at any moment plays crucial role in deciding schedulability. We propose a pseudo-boolean satisfiability (PB-SAT) based approach for solving this schedulability problem of power modes for a collection of tasks. We show that in majority of useful cases, the problem can be encoded using linear constraints only and thus becomes an instance of PB-SAT problem. We also show how we can find out a mode allocation using PB-SAT approach that ensures minimum power consumption, but never viloates any temporal constraint. We also propose a binary search based approach with PB-SAT as its core, how we can find out the bare minimum value of the battery peak power that will allow a power mode allocation to the tasks without violating its temporal constraints. Results show that the approach gives acceptable results in many cases.
Citation:
Sayak Ray, Pallab Dasgupta, P. P. Chakrabarti, "A New Pseudo-Boolean Satisfiability based approach to Power Mode Schedulability Analysis," vlsid, pp.95-102, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||