We propose a sequential built-in self-test (BIST) hardware pattern generator using Haar wavelets, linear feedback shift registers (LFSRs), modulation, correlation and biasing hardware that produces higher fault efficiencies (FEs) than existing sequential BIST methods. We generate random bit sequences for primary inputs (PIs), which are modulated by Haar wavelets. Our correlator may substitute a highly-correlated PI bit stream for the actual bit stream for this PI. Finally, the bit stream is biased toward a particular probability of generating a 1 input before being fed to the PI. Results on ISCAS ?89 benchmarks show that this BIST method produces 96.77% FE for circuits without resettable flip-flops, and 99.41% (upper-bound) FE, for those with resettable flip-flops. Upadhyayula and Bushnell [16] only attained 81.4% FE. Our method is implemented in hardware as opposed to Giani et al. [9] who have systemon- a-chip (SoC) implementations that require an on-board microprocessor and cannot perform at-speed test. Our hardware overhead is 9.01%, much less than Giani et al.?s method. Compared to Pomeranz and Reddy?s work [14], we achieved 95.69% FE, compared with 95.01% for them, and on the circuits where they presented results, we have 66.3% hardware overhead versus 234.1% for them.