The details of the power distribution of state of the art CMOS chips (e.g., local regions of high power (or hotspots), which disproportionally drive up junction temperatures) can have a severe impact on reliability, manufacturing yield and chip performances. In this paper we discuss the results of a recently developed technique (Spatially-resolved imaging of micro-processor power (SIMP)), which can measure power and temperature distributions of high power chips (e.g., microprocessors) under full operating conditions. Specifically, we present detailed microprocessor power distributions for different workloads with and without power/thermal management. The data yields a more comprehensive understanding of the relationships between hotspots and the respective designs, layouts, floorplans, micro-architectures and thermal/power management schemes, which is discussed in detail.