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20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07)
Speeding up Monte-Carlo Simulation for Statistical Timing Analysis of Digital Integrated Circuits
Bangalore, India
January 06-January 10
ISBN: 0-7695-2762-0
ASCII Text
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Srinath R. Naidu, "Speeding up Monte-Carlo Simulation for Statistical Timing Analysis of Digital Integrated Circuits," VLSI Design, International Conference on, pp. 265-270, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007.
 
 
BibTex
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@article{ 10.1109/VLSID.2007.147,
author = {Srinath R. Naidu},
title = {Speeding up Monte-Carlo Simulation for Statistical Timing Analysis of Digital Integrated Circuits},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2007},
issn = {1063-9667},
pages = {265-270},
doi = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2007.147},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - Speeding up Monte-Carlo Simulation for Statistical Timing Analysis of Digital Integrated Circuits
SN - 1063-9667
SP265
EP270
A1 - Srinath R. Naidu,
PY - 2007
KW - null
VL - 0
JA - VLSI Design, International Conference on
ER -
 
Srinath R. Naidu, Magma Design Automation India Pvt. Ltd., Bangalore, India
This paper presents a pair of novel techniques to speed-up path-based Monte-Carlo simulation for statistical timing analysis of digital integrated circuits with no loss of accuracy. The presented techniques can be used in isolation or they could be used together. Both techniques can be readily implemented in any statistical timing framework. We compare our proposed Monte-Carlo simulation with traditional Monte-Carlo simulation in a rigourous framework and show that the new method is up to 2 times as efficient as the traditional method.
Citation:
Srinath R. Naidu, "Speeding up Monte-Carlo Simulation for Statistical Timing Analysis of Digital Integrated Circuits," vlsid, pp.265-270, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007
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