20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07)
Reusing Learned Information in SAT-based ATPG
Bangalore, India
January 06-January 10
ISBN: 0-7695-2762-0
Tim Warode, University of Bremen, 28359 Bremen, Germany
The robustness of engines for ATPG has to be improved to cope with the growing size of circuits. Recently, SAT-based ATPG approaches have been shown to be very robust even on large industrial circuits. Here, we propose techniques to further improve the efficiency by embedding learning techniques in a SATbased ATPG engine. We provide a heuristic to apply incremental SAT when enumerating faults and a technique to apply circuit-based learning where incremental SAT is not applicable. The correctness of circuit-based learning is proven. Experimental results on large benchmarks show the efficiency.
Citation:
Gorschwin Fey, Tim Warode, Rolf Drechsler, "Reusing Learned Information in SAT-based ATPG," vlsid, pp.69-76, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007