While CMOS technology has served semiconductor industry marvelously (by allowing nearly exponential increase in performance and device integration density), it faces some major roadblocks at sub-90nm process nodes due to the intrinsic physical limitations of the devices. One of the major barriers that the CMOS devices face at nanometer scale is increasing process parameter variations. Due to limitations of the fabrication process (e.g. sub-wavelength lithography and etching) and variations in the number of dopants in the channel of short channel devices, device parameters such as length (L), width 0, oxide thickness (T,), threshold voltage (VTH) etc. suffer large variations. Variations in the device parameters, both systematic and random, translate into variations in circuit parameters like delay and leakage power, leading to loss in parametric yield. To deal with increasing parameter variations, it is important to accurately model the impact of device parameter variations at circuit level and develop process-tolerant design techniques for both logic and memory. This article analyzes the impact of process parameter variations on logic circuits and memory and focuses on some major works in the area of process-tolerant design methodology at circuit/architecture level.