20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07)
Parallelization of DC Analysis through Multiport Decomposition
Bangalore, India
January 06-January 10
ISBN: 0-7695-2762-0
Physical problems offer scope for macro level parallelization of solution by their essential structure. For parallelization of electrical network simulation, the most natural structure based method is that of Multiport Decomposition. In this paper this method is used for the simulation of electrical networks consisting of resistances, voltage and current sources using a distributed cluster of weakly coupled processors. At the two levels in which equations are solved in this method we have used sparse LU for both levels in the first scheme and sparse LU in the inner level and Conjugate Gradient in the outer level in the second scheme. Results are presented for planar networks, for the cases where the number of slave processors are 1 and 2, and for circuit sizes upto 8.2 million nodes and 16.4 million edges using 8 slave processors. We use a cluster of Pentium IV processors linked through a 10/100MBPS Ethernet switch.
Citation:
Gaurav Trivedi, Madhav P. Desai, H. Narayanan, "Parallelization of DC Analysis through Multiport Decomposition," vlsid, pp.863-868, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007
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