An effective technique for reducing leakage currents in an SRAM cell in standby mode is by reducing effective supply voltage across the cell. It is shown that raising of negative supply voltage level (VSS) is more effective in reducing subthreshold leakage currents, while reduction in positive supply voltage level (VDD) has relatively larger impact on gate leakage currents. As a result, for a fixed effective supply voltage across the cell in standby mode, there is an optimum combination of supply rails that minimizes leakage currents depending on the relative importance of subthreshold and gate leakage currents. Simulation results based on BPTM (Berkeley Predictive Technology Model) are presented that show that for a net voltage across the cell of 0.5V, supply voltages (VDD, VSS) of (0.35, 0.85), (0.25, 0.75) and (0.1, 0.6) yield minimum leakage currents in 90nm, 65nm and 45nm technology nodes respectively.