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20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07)
Modified Stability Checking for On-line Error Detection
Bangalore, India
January 06-January 10
ISBN: 0-7695-2762-0
Satish Yada, Indian Institute of Science, Bangalore, India.
Bharadwaj Amrutur, Indian Institute of Science, Bangalore, India.
Rubin A. Parekhji, Texas Instruments (India) Pvt. Ltd., Bangalore, India.
We propose a unified error detection technique, based on stability checking, for on-line detection of delay, crosstalk and transient faults in combinational circuits and SEUs in sequential elements. Our method, called Modified Stability Checking (MSC), overcomes the limitations of the earlier stability checking methods. We also propose a novel checker circuit to realize this scheme. The checker is self-checking for a wide set of realistic internal faults including transient faults. Extensive circuit simulations have been done to characterize the checker circuit. A prototype checker circuit for a 1mm2 standard cell array has been implemented in a 0.13um process.
Index Terms:
Concurrent testing, delay faults, crosstalk faults and transient faults, SEU testing, modified stability checking, self-checking circuits, on-line error detection.
Citation:
Satish Yada, Bharadwaj Amrutur, Rubin A. Parekhji, "Modified Stability Checking for On-line Error Detection," vlsid, pp.787-792, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007
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