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20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07)
Modeling Techniques for Formal Verification of BIST Controllers and Their Integration into SOC Designs
Bangalore, India
January 06-January 10
ISBN: 0-7695-2762-0
ASCII Text
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Subir K. Roy, Rubin A. Parekhji, "Modeling Techniques for Formal Verification of BIST Controllers and Their Integration into SOC Designs," VLSI Design, International Conference on, pp. 364-372, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007.
 
 
BibTex
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@article{ 10.1109/VLSID.2007.112,
author = {Subir K. Roy and Rubin A. Parekhji},
title = {Modeling Techniques for Formal Verification of BIST Controllers and Their Integration into SOC Designs},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2007},
issn = {1063-9667},
pages = {364-372},
doi = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2007.112},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - Modeling Techniques for Formal Verification of BIST Controllers and Their Integration into SOC Designs
SN - 1063-9667
SP364
EP372
A1 - Subir K. Roy,
A1 - Rubin A. Parekhji,
PY - 2007
KW - null
VL - 0
JA - VLSI Design, International Conference on
ER -
 
Subir K. Roy, Texas Instruments (India) Pvt. Ltd., C. V. Raman Nagar, Bangalore 560093, India.
Rubin A. Parekhji, Texas Instruments (India) Pvt. Ltd., C. V. Raman Nagar, Bangalore 560093, India.
This paper describes the methods and challenges for modeling BIST logic in complex SOCs to enable their verification using formal techniques. The main contributions of this paper are: (a) application of symbolic model checking to BIST logic verification, (b) abstraction and modeling of sequential blocks such as memories, data-loggers, scan chains and LFSRs to enable property based formal verification, (c) automated generation of re-usable hookup logic properties, and (d) experimental results to highlight the benefits of the proposed t echniques.
Citation:
Subir K. Roy, Rubin A. Parekhji, "Modeling Techniques for Formal Verification of BIST Controllers and Their Integration into SOC Designs," vlsid, pp.364-372, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007
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