A Fast and Accurate approach for Full Chip Leakage Analysis of Nano-scale circuits considering Intra-die Correlations

V
VLSID
2007
20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07)
Abstract - A Fast and Accurate approach for Full Chip Leakage Analysis of Nano-scale circuits considering Intra-die Correlations

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	Similar Articles Articles by Sarvesh Bhardwaj Articles by Sarma Vrudhula

20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07)

Bangalore, India

January 06-January 10

ISBN: 0-7695-2762-0

	ASCII Text	x
	Sarvesh Bhardwaj, Sarma Vrudhula, "A Fast and Accurate approach for Full Chip Leakage Analysis of Nano-scale circuits considering Intra-die Correlations," VLSI Design, International Conference on, pp. 589-594, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007.

	BibTex	x
	@article{ 10.1109/VLSID.2007.11, author = {Sarvesh Bhardwaj and Sarma Vrudhula}, title = {A Fast and Accurate approach for Full Chip Leakage Analysis of Nano-scale circuits considering Intra-die Correlations}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2007}, issn = {1063-9667}, pages = {589-594}, doi = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2007.11}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - A Fast and Accurate approach for Full Chip Leakage Analysis of Nano-scale circuits considering Intra-die Correlations SN - 1063-9667 SP589 EP594 A1 - Sarvesh Bhardwaj, A1 - Sarma Vrudhula, PY - 2007 KW - null VL - 0 JA - VLSI Design, International Conference on ER -

Sarvesh Bhardwaj, Arizona State University, Tempe, AZ

Sarma Vrudhula, Arizona State University, Tempe, AZ

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VLSID.2007.11

This paper presents an accurate and efficient approach for estimating the full chip leakage in the presence of intra-die variations. We use an accurate model for leakage in which the leakage is exponentially dependent on a quadratic function of the device parameters. The intradie correlations in the device parameters are accounted by representing the parameters in terms of abstract independent random variables using Karhunen-Lo`eve Expansion. The total circuit leakage is computed using an efficient sum operation. Our results on ISCAS89 benchmark circuits show a speed up of up to 500? compared to Monte Carlo analysis, with average percentage difference in mean and variance being less than 1.5%.

Citation:

Sarvesh Bhardwaj, Sarma Vrudhula, "A Fast and Accurate approach for Full Chip Leakage Analysis of Nano-scale circuits considering Intra-die Correlations," vlsid, pp.589-594, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007

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