Modeling and Analysis of Noise Margin in SET Logic

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	Similar Articles Articles by Chaitanya Sathe Articles by Santanu Mahapatra

20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07)

Bangalore, India

January 06-January 10

ISBN: 0-7695-2762-0

	ASCII Text	x
	Chaitanya Sathe, Santanu Mahapatra, "Modeling and Analysis of Noise Margin in SET Logic," VLSI Design, International Conference on, pp. 207-214, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007.

	BibTex	x
	@article{ 10.1109/VLSID.2007.109, author = {Chaitanya Sathe and Santanu Mahapatra}, title = {Modeling and Analysis of Noise Margin in SET Logic}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2007}, issn = {1063-9667}, pages = {207-214}, doi = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2007.109}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Modeling and Analysis of Noise Margin in SET Logic SN - 1063-9667 SP207 EP214 A1 - Chaitanya Sathe, A1 - Santanu Mahapatra, PY - 2007 KW - null VL - 0 JA - VLSI Design, International Conference on ER -

Chaitanya Sathe, Indian Institute of Science

Santanu Mahapatra, Indian Institute of Science

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VLSID.2007.109

In this paper the Static Noise Margin for SET (Single Electron Transistor) logic is defined and compact models for the noise margin are developed by making use of the MIB (Mahapatra-Ionescu-Banerjee) model. The variation of the noise margin with temperature and background charge is also studied. A chain of SET inverters is simulated to validate the definition of various logic levels (like VIH, VOH etc) and Noise Margin. Finally the noise immunity of SET logic is compared with current CMOS logic.

Citation:

Chaitanya Sathe, Santanu Mahapatra, "Modeling and Analysis of Noise Margin in SET Logic," vlsid, pp.207-214, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007

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