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20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07)
Low Power Sensor Node for a Wireless Sensor Network
Bangalore, India
January 06-January 10
ISBN: 0-7695-2762-0
Akepati Sravan, IIT Kharagpur, India
Sujan Kundu, IIT Kharagpur, India
Ajit Pal, IIT Kharagpur, India
Wireless sensor networks are finding widespread use in diverse applications. The sensor nodes, which are also called as motes, are getting smaller, but their battery charge density is not getting increased in the same ratio. Since the life of a sensor network depends on the life of the sensor nodes, the lifetime of the sensor nodes have to be maximized. This can happen if the battery lasts long. In this paper, we introduce a power-aware sensor node architecture and a battery-aware task scheduling algorithm that uses both Dynamic Voltage Scaling (DVS) and Reverse Body Biasing (RBB) to maximize the battery life time. Significant reduction in energy requirement is possible based on the proposed approach.
Citation:
Akepati Sravan, Sujan Kundu, Ajit Pal, "Low Power Sensor Node for a Wireless Sensor Network," vlsid, pp.445-450, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007
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