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19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06)
High Performance MTCMOS Technique for Leakage Reduction in Hybrid SOI-Epitaxial Technologies with Enhanced-Mobility PFET Header
Hyderabad, India
January 03-January 07
ISBN: 0-7695-2502-4
ASCII Text
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Koushik K. Das, Shih-Hsien Lo, Ching-Te Chuang, "High Performance MTCMOS Technique for Leakage Reduction in Hybrid SOI-Epitaxial Technologies with Enhanced-Mobility PFET Header," VLSI Design, International Conference on, pp. 758-761, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006.
 
 
BibTex
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@article{ 10.1109/VLSID.2006.97,
author = {Koushik K. Das and Shih-Hsien Lo and Ching-Te Chuang},
title = {High Performance MTCMOS Technique for Leakage Reduction in Hybrid SOI-Epitaxial Technologies with Enhanced-Mobility PFET Header},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2006},
issn = {1063-9667},
pages = {758-761},
doi = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2006.97},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - High Performance MTCMOS Technique for Leakage Reduction in Hybrid SOI-Epitaxial Technologies with Enhanced-Mobility PFET Header
SN - 1063-9667
SP758
EP761
A1 - Koushik K. Das,
A1 - Shih-Hsien Lo,
A1 - Ching-Te Chuang,
PY - 2006
KW - null
VL - 0
JA - VLSI Design, International Conference on
ER -
 
Koushik K. Das, IBM TJ Watson Research Center
Shih-Hsien Lo, IBM TJ Watson Research Center
Ching-Te Chuang, IBM TJ Watson Research Center
Power management has become a key constraint in the design of modern digital VLSI chips. Moreover, with minimum transistor dimensions reaching 100-nm and below, traditional scaling has slowed down. The ITRS roadmap has indicated that device mobility enhancement would be necessary to maintain the generational performance improvement in the sub-100nm VLSI era. This paper presents a comprehensive analysis of the popular low-leakage power MTCMOS circuit technique in various emerging technologies with enhanced-mobility PFETs.
Citation:
Koushik K. Das, Shih-Hsien Lo, Ching-Te Chuang, "High Performance MTCMOS Technique for Leakage Reduction in Hybrid SOI-Epitaxial Technologies with Enhanced-Mobility PFET Header," vlsid, pp.758-761, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006
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