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19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06)
Heterogeneous Floorplanning for FPGAs
Hyderabad, India
January 03-January 07
ISBN: 0-7695-2502-4
ASCII Text
x 
 
Yan Feng, Dinesh P. Mehta, "Heterogeneous Floorplanning for FPGAs," VLSI Design, International Conference on, pp. 257-262, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006.
 
 
BibTex
x
 
@article{ 10.1109/VLSID.2006.96,
author = {Yan Feng and Dinesh P. Mehta},
title = {Heterogeneous Floorplanning for FPGAs},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2006},
issn = {1063-9667},
pages = {257-262},
doi = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2006.96},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - Heterogeneous Floorplanning for FPGAs
SN - 1063-9667
SP257
EP262
A1 - Yan Feng,
A1 - Dinesh P. Mehta,
PY - 2006
KW - null
VL - 0
JA - VLSI Design, International Conference on
ER -
 
Yan Feng, University of Minnesota
Dinesh P. Mehta, Colorado School of Mines
The large size of modern FPGAs has caused researchers to consider deploying hierarchical techniques in their design. In this paper, we consider the floorplanning of FPGAs. We present a two-step approach for the floorplanning of modern FPGAs that we believe is cleaner and more versatile than recent floorplanners. The steps, based on resource-aware fixed outline simulated annealing and constrained floorplanning, are adapted to address the heterogeneous nature of FPGA floorplanning. Experiments demonstrate the viability of our approach.
Citation:
Yan Feng, Dinesh P. Mehta, "Heterogeneous Floorplanning for FPGAs," vlsid, pp.257-262, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006
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