loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06)
Frame Based Fair Multiprocessor Scheduler: A Fast Fair Algorithm for Real-Time Embedded Systems
Hyderabad, India
January 03-January 07
ISBN: 0-7695-2502-4
ASCII Text
x 
 
Arnab Sarkar, P. P. Chakrabarti, Rajeev Kumar, "Frame Based Fair Multiprocessor Scheduler: A Fast Fair Algorithm for Real-Time Embedded Systems," VLSI Design, International Conference on, pp. 677-682, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006.
 
 
BibTex
x
 
@article{ 10.1109/VLSID.2006.90,
author = {Arnab Sarkar and P. P. Chakrabarti and Rajeev Kumar},
title = {Frame Based Fair Multiprocessor Scheduler: A Fast Fair Algorithm for Real-Time Embedded Systems},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2006},
issn = {1063-9667},
pages = {677-682},
doi = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2006.90},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - Frame Based Fair Multiprocessor Scheduler: A Fast Fair Algorithm for Real-Time Embedded Systems
SN - 1063-9667
SP677
EP682
A1 - Arnab Sarkar,
A1 - P. P. Chakrabarti,
A1 - Rajeev Kumar,
PY - 2006
KW - null
VL - 0
JA - VLSI Design, International Conference on
ER -
 
Arnab Sarkar, Indian Institute of Technology - Kharagpur
P. P. Chakrabarti, Indian Institute of Technology - Kharagpur
Rajeev Kumar, Indian Institute of Technology - Kharagpur
This paper presents Frame Based Fair Multiprocessor Scheduler (FBFMS) which provides accurate real-time proportional fair scheduling for a set of dynamic tasks on a symmetric multiprocessor environment with O(1) scheduling overhead. FBFMS meets these seemingly contradictory goals by applying the benefits of Virtual Time Round- Robin scheduling mechanism along with a frame based scheduling approach. Simulation results show that the algorithm provides 2.5 to 26 times speedup (over O(lg n) complexity schedulers) with distortion in fairness less than 1% in most cases, and less than 15% in the worst case.
Citation:
Arnab Sarkar, P. P. Chakrabarti, Rajeev Kumar, "Frame Based Fair Multiprocessor Scheduler: A Fast Fair Algorithm for Real-Time Embedded Systems," vlsid, pp.677-682, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006
Usage of this product signifies your acceptance of the Terms of Use.