A High-Performance VLSI Architecture for Advanced Encryption Standard (AES) Algorithm

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Naga M. Kosaraju Articles by Murali Varanasi Articles by Saraju P. Mohanty

19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06)

Hyderabad, India

January 03-January 07

ISBN: 0-7695-2502-4

	ASCII Text	x
	Naga M. Kosaraju, Murali Varanasi, Saraju P. Mohanty, "A High-Performance VLSI Architecture for Advanced Encryption Standard (AES) Algorithm," VLSI Design, International Conference on, pp. 481-484, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006.

	BibTex	x
	@article{ 10.1109/VLSID.2006.9, author = {Naga M. Kosaraju and Murali Varanasi and Saraju P. Mohanty}, title = {A High-Performance VLSI Architecture for Advanced Encryption Standard (AES) Algorithm}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2006}, issn = {1063-9667}, pages = {481-484}, doi = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2006.9}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - A High-Performance VLSI Architecture for Advanced Encryption Standard (AES) Algorithm SN - 1063-9667 SP481 EP484 A1 - Naga M. Kosaraju, A1 - Murali Varanasi, A1 - Saraju P. Mohanty, PY - 2006 KW - null VL - 0 JA - VLSI Design, International Conference on ER -

Naga M. Kosaraju, University of South Florida

Murali Varanasi, University of North Texas

Saraju P. Mohanty, University of North Texas

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VLSID.2006.9

In this paper we present a high-performance, high throughput, and area efficient architecture for the VLSI implementation of the AES algorithm. The subkeys, required for each round of the Rijndael algorithm, are generated in real-time by the key-scheduler module by expanding the initial secret key, thus reducing the amount of storage for buffering. Moreover, pipelining is used after each standard round to enhance the throughput. A prototype chip implemented using 0.35? CMOS technology resulted in a throughput of 232Mbps for iterative architecture and 1.83Gbps for pipelining architecture.

Citation:

Naga M. Kosaraju, Murali Varanasi, Saraju P. Mohanty, "A High-Performance VLSI Architecture for Advanced Encryption Standard (AES) Algorithm," vlsid, pp.481-484, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.