19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06)
Dynamic Template Generation for Resource Sharing in Control and Data Flow Graphs
Hyderabad, India
January 03-January 07
ISBN: 0-7695-2502-4
High-level synthesis compilers often produce reoccurring patterns in intermediate CDFGs during translation. By identifying large reoccurring patterns, one may reduce area and communication overhead by efficiently reusing hardware for multiple operations. This paper presents an algorithm for dynamically generating templates of reoccurring patterns for resource sharing in CDFGs. Results show 40-80% resource reduction using small, incremental template growth, and variations within a 5% margin among varying look-ahead depths.
Citation:
David C. Zaretsky, Gaurav Mittal, Robert P. Dick, Prith Banerjee, "Dynamic Template Generation for Resource Sharing in Control and Data Flow Graphs," vlsid, pp.465-468, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006