Checking Nested Properties Using Bounded Model Checking and Sequential ATPG

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19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06)

Hyderabad, India

January 03-January 07

ISBN: 0-7695-2502-4

	ASCII Text	x
	Qiang Qiang, Daniel G. Saab, Jacob A. Abraham, "Checking Nested Properties Using Bounded Model Checking and Sequential ATPG," VLSI Design, International Conference on, pp. 225-230, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006.

	BibTex	x
	@article{ 10.1109/VLSID.2006.58, author = {Qiang Qiang and Daniel G. Saab and Jacob A. Abraham}, title = {Checking Nested Properties Using Bounded Model Checking and Sequential ATPG}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2006}, issn = {1063-9667}, pages = {225-230}, doi = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2006.58}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Checking Nested Properties Using Bounded Model Checking and Sequential ATPG SN - 1063-9667 SP225 EP230 A1 - Qiang Qiang, A1 - Daniel G. Saab, A1 - Jacob A. Abraham, PY - 2006 KW - null VL - 0 JA - VLSI Design, International Conference on ER -

Qiang Qiang, Case Western Reserve University

Daniel G. Saab, Case Western Reserve University

Jacob A. Abraham, University of Texas at Austin

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VLSID.2006.58

This paper develops a novel approach to formally verify nested VLSI circuit properties, using bounded model checking and gate-level sequential ATPG tools. This approach improves the verification quality by devising an algorithm that checks nested realistic properties. This makes ATPG verification based tools applicable to realistic properties. We also show that the performance of our approach is superior when compared to SAT-based techniques in both efficiency and capacity, especially for large bounds and for complex properties.

Citation:

Qiang Qiang, Daniel G. Saab, Jacob A. Abraham, "Checking Nested Properties Using Bounded Model Checking and Sequential ATPG," vlsid, pp.225-230, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006

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