19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06)
Bounding Supply Noise Induced Path Delay Variation Using a Relaxation Approach
Hyderabad, India
January 03-January 07
ISBN: 0-7695-2502-4
This paper presents a general ILP model for analyzing the supply noise induced worst path delay variation. The proposed model can address various modes of supply noise analysis: function based, two-vector pattern based, or multiple cycle analysis, additionally capable of including user-specified constraints. The formulated ILP problem is solved via a relaxation approach, which produces a conservative upper-bound estimation to the worst path delay variation at any iteration. The paper applies sub-gradient optimization to improve those upper bounds. Experimentations have demonstrated the efficiency of the proposed approach, by comparisons with a commercial ILP solver and traditional supply noise modeling approaches.
Citation:
Baohua Wang, Pinaki Mazumder, "Bounding Supply Noise Induced Path Delay Variation Using a Relaxation Approach," vlsid, pp.349-354, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006