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19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06)
Apriori Formal Coverage Analysis for Protocol Properties
Hyderabad, India
January 03-January 07
ISBN: 0-7695-2502-4
Praveen Tiwari, Texas Instruments (India) Pvt. Ltd.
Saptarshi Biswas, Texas Instruments (India) Pvt. Ltd.
Raj S. Mitra, Texas Instruments (India) Pvt. Ltd.
Protocol compliance verification is a key component of the overall SOC verification process. Formal techniques have been applied to achieve high confidence in such verification, but the quality of the protocol properties themselves is not subjected to this rigor of verification. Determining the formal coverage of the protocol properties with respect to an implementation is not sufficient, because it may not have captured the full scope of the protocol. We propose a technique to solve this important problem, by formally covering a protocol?s properties independent of the implementation. The coverage is determined with respect to the protocol specification (i.e. its semantics), which is captured as a State Transition Graph (STG). Developing an STG for a complex protocol is a non-trivial task; in this paper we also propose techniques to efficiently model complex protocol features like pipelining and threading. Results for OCP and AHB are shown to illustrate our approach.
Citation:
Praveen Tiwari, Saptarshi Biswas, Raj S. Mitra, "Apriori Formal Coverage Analysis for Protocol Properties," vlsid, pp.231-236, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006
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