19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06) An Asynchronous Interconnect Architecture for Device Security Enhancement Hyderabad, India January 03-January 07 ISBN: 0-7695-2502-4
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VLSID.2006.40
We present a new style of long-distance, on-chip inter-connect, based loosely on the asynchronous GasP architecture. It has a number of advantages over conventional designs, the most prominent being security enhancements, a reduction in the number of wires required, no need for clock distribution or packetization, and ease of composition. We give some sample throughput and latency figures from simulation on a 0.18µm technology and show that it is viable for use with modern interconnect requirements, is of low complexity and has a lower area requirement than parallel interconnect over distances as short as 1mm.
Citation:
Simon Hollis, Simon W. Moore, "An Asynchronous Interconnect Architecture for Device Security Enhancement," vlsid, pp.209-215, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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