This paper deals with a monolithic dynamic voltage comparator with sampling speed up to 3.8GHz and a resolution of 8-bit. To improve the power-speed tradeoff, the front-end pre-amplifier is being designed with high f_T (80GHz) Si-SiGe Heterojunction Bipolar Transistor (HBT) for higher speed while the dynamic latch along with the output buffer is implemented in 0.25um standard CMOS process to keep the power level low. To operate the CMOS latch at 3.8GHz sampling rate, a tailor made 3- Φ clocking scheme is employed where the reset time of the latch falls up to 45ps in the reset mode. In the tracking mode, controlled decision transferring is done from pre-amplifier to the latch. At the latch output, a buffer with hysteresis is used to overcome the switching noise of latch and produce sharp, well defined digital data. The active power consumption by the core comparator is ∼9mW and it takes a core area of ∼0.017 mm².