A 1.2Gb/s/channel inductive inter-chip wireless interconnect is reported in ISSCC 2004. For high data bandwidth in this scheme, high density inductor layout is required, but closer layout of inductors on chip also increases the crosstalk between channels. In this paper a theory is introduced to reduce the crosstalk between wireless channels based on the inverse matrix, which in turn helps in reducing the pitch of the inductor layout. The simulations were done for a communication distance of 15 µm and for varying inductor pitch layout from 10 µm to 50 µm. Simulink simulations show that for the same Signal to Noise Ratio (SNR) the Bit Error Rate (BER) can be improved for the given pitch. Circuit implementations are proposed and Spice simulations show that the pitch of the inductor layout can be decreased only with the help of change in layout from 25 µm to 15 µm for SNR of 15db.