This paper describes a wide range, area efficient, high resolution Time to Digital Converter (TDC), which has applications in digital frequency synthesizers used in wireless applications. The proposed architecture removes the need for long Vernier delay stages while measuring large phase differences using the Vernier delay line method. Resolution of a Vernier TDC is extremely susceptible to process, voltage and temperature (PVT) variations. The proposed compact implementation thereby minimizes the susceptibility of the TDC resolution to PVT variations. In the proposed method, time is digitized to the nearest multiple of a constant buffer delay and finer time digitization, less than one buffer delay is carried out using Vernier delay line. The TDC Circuit was designed and implemented in 0.18?m CMOS technology and achieves a resolution less than 10ps. The resolution variation in all the process corners was analyzed and the simulation results, layout implementation details and the linearity plots are presented.