Backend planning for SoCs needs to account for power pads and pins for different power domains. IO power pad requirements for high speed interfaces, are directly dependent on the worst case switching of output buffers. This work proposes an algorithm that takes switching activity patterns of a set of output buffers for an interface and generates an optimized IO power and ground pad locations. Optimisation is achieved by splitting the spatial locations of the drivers into smaller groups and solving pad requirement problem for each of the groups. Ground bounce is the main component based on which the pad count is estimated. Special requirements like multiple power domains, different packages (TQFP, BGA) etc, have also been addressed. Its been shown by simulations that up to 20% reduction in pad count can be achieved if switching patterns are available.