loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06)
Solving Thermal Problems of Hot Chips Using Voronoi Diagrams
Hyderabad, India
January 03-January 07
ISBN: 0-7695-2502-4
ASCII Text
x 
 
S. Majumder, B. B. Bhattacharya, "Solving Thermal Problems of Hot Chips Using Voronoi Diagrams," VLSI Design, International Conference on, pp. 545-548, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006.
 
 
BibTex
x
 
@article{ 10.1109/VLSID.2006.150,
author = {S. Majumder and B. B. Bhattacharya},
title = {Solving Thermal Problems of Hot Chips Using Voronoi Diagrams},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2006},
issn = {1063-9667},
pages = {545-548},
doi = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2006.150},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - Solving Thermal Problems of Hot Chips Using Voronoi Diagrams
SN - 1063-9667
SP545
EP548
A1 - S. Majumder,
A1 - B. B. Bhattacharya,
PY - 2006
KW - null
VL - 0
JA - VLSI Design, International Conference on
ER -
 
S. Majumder, International Institute of Information Technology
B. B. Bhattacharya, Indian Statistical Institute
A geometric simulation based method is proposed in this paper, for fast identification of hot spots and zones on a chip. Given a set of points on the chip floor with their respective thermal strengths, a multiplicatively weighted Voronoi diagram is used to mark the zones of the chip that are under potential thermal threat. For further accurate prediction of hot spots and zones on the chip, simulation is performed only in these regions. This method provides a significant amount of savings in simulation time. Next a simple procedure is suggested to disperse some of the source points on the chip so that the thermal profile of the critical zones may go down below the threshold (safe) level.
Citation:
S. Majumder, B. B. Bhattacharya, "Solving Thermal Problems of Hot Chips Using Voronoi Diagrams," vlsid, pp.545-548, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006
Usage of this product signifies your acceptance of the Terms of Use.