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19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06)
SEAT-LA: A Soft Error Analysis Tool for Combinational Logic
Hyderabad, India
January 03-January 07
ISBN: 0-7695-2502-4
R. Rajaraman, Penn State University
J. S. Kim, Penn State University
N. Vijaykrishnan, Penn State University
Y. Xie, Penn State University
M. J. Irwin, Penn State University
Radiation induced soft errors in combinational logic is expected to become as important as directly induced errors on state elements. Consequently, it has become important to develop techniques to quickly and accurately predict soft error rates (SER) in logic circuits. In this paper, we propose a new approach, which can be applied to designs that use cell libraries characterized for soft error analysis and utilizes analytical equations to model the propagation of a voltage pulse to the input of a state element. The average error of the SER estimates using our approach compared to the estimates obtained using circuit level simulations is 6.5% while providing an average speed up of 15000. We have demonstrated the scalability of our approach using designs from the ISCAS-85 benchmarks.
Citation:
R. Rajaraman, J. S. Kim, N. Vijaykrishnan, Y. Xie, M. J. Irwin, "SEAT-LA: A Soft Error Analysis Tool for Combinational Logic," vlsid, pp.499-502, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006
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