The total time to execute an application, the energy consumed, and the flexibility to manage a large set of applications are among the most important performance parameters used to measure the quality of a computing system. Superior architectures with flexible reconfigurable arrays lead to innovation beyond the limits of traditional silicon. The incorporation of on-chip reconfigurable computing elements generally improves execution time. However, the amount of energy consumed to deliver the required level of performance is an important consideration, to prolong the battery life in portable and mobile devices. In this paper, we have proposed and designed a novel scalable array architecture and explored the performance and energy trade-offs for various applications by scaling various system parameters like hardware resources, operational granularity, and voltage supply. The scalable coprocessor design for mapping Discrete Cosine Transform (DCT) is implemented with 8 taps resulting in an area of 0.0024