19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06) Performance Measurement and Improvement of Asymmetric Three-Tr. Cell (ATC) DRAM toward 0.3V Memory Array Operation Hyderabad, India January 03-January 07 ISBN: 0-7695-2502-4
For a Mb-class embedded memory, asymmetric three-transistor cell (ATC) DRAM has been reported. The memory cell is a non-destructive-read type and the memory array runs at 0.5V, half the voltage of normal peripheral circuits, on a 90nm generic CMOS logic process. A sense amplifier designed for this DRAM is insensitive to input capacitance and can operate with a power supply voltage as low as 0.5V. Through our experiments, we have identified three ways to improve the ATC DRAM. And these improvements enable the sense time to be 6.3ns and refresh power consumption to be 45?W with 0.3V memory array voltage by simulation results.
Citation:
Motoi Ichihashi, Haruki Toda, "Performance Measurement and Improvement of Asymmetric Three-Tr. Cell (ATC) DRAM toward 0.3V Memory Array Operation," vlsid, pp.487-490, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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