This paper presents a novel methodology of global interconnect optimization for high performance integrated circuits. The impacts of interconnect width and spacing on various performances such as delay, power dissipation and chip area are analyzed. A tradeoff exists between delay and power dissipation of global interconnects with repeaters insertion. Optimum line width is determined by the minimum delay-power product which is defined as a figure of merit (FOM). As the silicon area and wireability of chip are taken into account, the delay-power-area product is introduced as another FOM to optimize the global interconnects. Optimizations of global interconnect size with different scenarios are applied for various International Technology Roadmap for Semiconductor technology nodes.