Interconnects are dominating VLSI circuit design in Deep sub-micron regime. Construction of global routing trees based on Required Arrival Times (RAT) has gained importance over the traditional problem of finding minimum-cost trees. Moreover, recent investigations on the fidelity of delay estimators indicate that the RAT trees with Manhattan distance delay, known as Linear RAT trees, are likely to be a viable alternative to buffered trees with Elmore delay model. This paper introduces the Linear RAT trees, discusses some related analysis, and proposes a heuristic method for constructing such trees.