loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06)
Improving the Performance of CAD Optimization Algorithms Using On-Line Meta-Level Control
Hyderabad, India
January 03-January 07
ISBN: 0-7695-2502-4
Sandip Aine, Indian Institute of Technology - Kharagpur
P. P. Chakrabarti, Indian Institute of Technology - Kharagpur
Rajeev Kumar, Indian Institute of Technology - Kharagpur
We present a profile based meta-reasoning model for parameter control of CAD algorithms working under constrained run-time. We also propose a unified framework, that can take informed decision about the time allocation and parameter adaptation of the algorithm, where there is no hard run-time constraints, instead the quality-time trade-off is expressed by a utility function. We use the proposed strategy to get an adaptive cooling schedule for the simulated annealing algorithm. Application on two classical NP-hard problems in the VLSI domain, namely, the standard cell placement problem and the circuit partitioning problem shows that significant improvement of quality can be achieved using a profile based control.
Citation:
Sandip Aine, P. P. Chakrabarti, Rajeev Kumar, "Improving the Performance of CAD Optimization Algorithms Using On-Line Meta-Level Control," vlsid, pp.683-688, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006
Usage of this product signifies your acceptance of the Terms of Use.