19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06) 16-Bit Segmented Type Current Steering DAC for Video Applications Hyderabad, India January 03-January 07 ISBN: 0-7695-2502-4
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VLSID.2006.1
In this paper, 16-bit, 50 MHz Current Steering DAC is designed. This DAC is implemented using TSMC 0.35 ?m technology. An optimum segmentation is done of 16-bits into binary and thermometric bits. The integral nonlinearity (INL) and differential non-linearity (DNL) is less than 0.3 LSB and 0.1 LSB respectively. It occupies only 0.06 mm2 area. The average total power consumption is 165 mW. A novel technique has been applied to reduce the glitch energy. The design is implemented with the matching requirements, required for current sources.
Index Terms:
Digital-to-Analog Conversion, Segmentation, Matching
Citation:
Gaurav Raja, Basabi Bhaumik, "16-Bit Segmented Type Current Steering DAC for Video Applications," vlsid, pp.63-68, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||