A Robust Architecture for Flip-Flops Tolerant to Soft-Errors and Transients from Combinational Circuits

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21st International Conference on VLSI Design (VLSI Design 2008)

Hyderabad, India

January 04-January 08

ISBN: 0-7695-3083-4

	ASCII Text	x
	Aditya Jagirdar, Roystein Oliveira, Tapan Jyoti Chakraborty, "A Robust Architecture for Flip-Flops Tolerant to Soft-Errors and Transients from Combinational Circuits," VLSI Design, International Conference on, pp. 39-44, 21st International Conference on VLSI Design (VLSI Design 2008), 2008.

	BibTex	x
	@article{ 10.1109/VLSI.2008.99, author = {Aditya Jagirdar and Roystein Oliveira and Tapan Jyoti Chakraborty}, title = {A Robust Architecture for Flip-Flops Tolerant to Soft-Errors and Transients from Combinational Circuits}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2008}, issn = {1063-9667}, pages = {39-44}, doi = {http://doi.ieeecomputersociety.org/10.1109/VLSI.2008.99}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - A Robust Architecture for Flip-Flops Tolerant to Soft-Errors and Transients from Combinational Circuits SN - 1063-9667 SP39 EP44 A1 - Aditya Jagirdar, A1 - Roystein Oliveira, A1 - Tapan Jyoti Chakraborty, PY - 2008 VL - 0 JA - VLSI Design, International Conference on ER -

Aditya Jagirdar

Roystein Oliveira

Tapan Jyoti Chakraborty

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VLSI.2008.99

Soft-errors are a leading cause of reliability issues dur- ing field operations. High-energy particles, either from cos- mic rays or from impurities in the packaging material can disrupt charge stored on the internal node capacitances leading to a malfunction of the device. Although this is usu- ally a temporary effect, it may lead to Silent Data Corrup- tion(SDC) when not detected in time. SDC may be detri- mental to many real-time commercial applications of the device and demands an effective solution that is cheap in terms of various design overheads. In this paper, we pro- pose two novel flip-flop designs aimed at detecting and cor- recting soft-errors and transients from combinational cir- cuits.Each design is optimized for a different set of con- straints and they have area overheads of 40% and 21% as compared to the standard industrial design of a scan flip- flop.

Citation:

Aditya Jagirdar, Roystein Oliveira, Tapan Jyoti Chakraborty, "A Robust Architecture for Flip-Flops Tolerant to Soft-Errors and Transients from Combinational Circuits," vlsid, pp.39-44, 21st International Conference on VLSI Design (VLSI Design 2008), 2008

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