VLSI floorplanning in the gigascale era must deal with multiple objectives including wiring congestion, performance and reliability. Genetic Algorithms lend themselves naturally to multi-objective optimization. In this paper, a multi-objective genetic algorithm is proposed for floorplanning that simultaneously minimizes area and total wirelength. The proposed genetic floorplanner is the first to use non-domination concepts to rank solutions. Two novel crossover operators are presented that build floorplans using good sub-floorplans. The efficiency of the proposed approach is illustrated by the 18% wirelength savings and 4.6% area savings obtained for the GSRC benchmarks and 26% wirelength savings for the MCNC benchmarks for a marginal 1.3% increase in area when compared to previous floorplanners that perform simultaneous area and wirelength minimization.