Design of Reversible Finite Field Arithmetic Circuits with Error Detection

V
VLSID
2008
21st International Conference on VLSI Design (VLSI Design 2008)
Abstract - Design of Reversible Finite Field Arithmetic Circuits with Error Detection

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	Similar Articles Articles by Jimson Mathew Articles by Hafizur Rahaman Articles by Babita R. Jose Articles by Dhiraj K. Pradhan

21st International Conference on VLSI Design (VLSI Design 2008)

Hyderabad, India

January 04-January 08

ISBN: 0-7695-3083-4

	ASCII Text	x
	Jimson Mathew, Hafizur Rahaman, Babita R. Jose, Dhiraj K. Pradhan, "Design of Reversible Finite Field Arithmetic Circuits with Error Detection," VLSI Design, International Conference on, pp. 453-459, 21st International Conference on VLSI Design (VLSI Design 2008), 2008.

	BibTex	x
	@article{ 10.1109/VLSI.2008.96, author = {Jimson Mathew and Hafizur Rahaman and Babita R. Jose and Dhiraj K. Pradhan}, title = {Design of Reversible Finite Field Arithmetic Circuits with Error Detection}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2008}, issn = {1063-9667}, pages = {453-459}, doi = {http://doi.ieeecomputersociety.org/10.1109/VLSI.2008.96}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Design of Reversible Finite Field Arithmetic Circuits with Error Detection SN - 1063-9667 SP453 EP459 A1 - Jimson Mathew, A1 - Hafizur Rahaman, A1 - Babita R. Jose, A1 - Dhiraj K. Pradhan, PY - 2008 VL - 0 JA - VLSI Design, International Conference on ER -

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VLSI.2008.96

we present a systematic method for the designing reversible arithmetic circuits for finite field or Galois fields of form GF(2?). It is shown that an adder over GF(2?) can be designed with m garbage bits and that of a PB multiplier with 2m garbage bits. To tackle the problem of errors in computation, we also extend the circuit with error detection feature. Gate count and technology oriented cost metrics are used for evaluation. The expression for the upper bound for gate size is also derived for special primitive polynomials. Our technique, when compared with existing CAD tool gives the same gate size and quantum cost.

Citation:

Jimson Mathew, Hafizur Rahaman, Babita R. Jose, Dhiraj K. Pradhan, "Design of Reversible Finite Field Arithmetic Circuits with Error Detection," vlsid, pp.453-459, 21st International Conference on VLSI Design (VLSI Design 2008), 2008

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