21st International Conference on VLSI Design (VLSI Design 2008) Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations Hyderabad, India January 04-January 08 ISBN: 0-7695-3083-4
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VLSI.2008.92
We investigate the feasibility of developing a comprehen- sive gate delay and slew models which incorporates output load, input edge slew, supply voltage, temperature, global process variations and local process variations all in the same model. We find that the standard polynomial mod- els cannot handle such a large heterogeneous set of input variables. We instead use neural networks, which are well known for their ability to approximate any arbitrary contin- uous function. Our initial experiments with a small subset of standard cell gates of an industrial 65nm library show promising results with error in mean less than 1% , error in standard deviation less than 3% and maximum error less than 11% as compared to SPICE for models covering 0.9- 1.1V of supply, -400C to 1250C of temperature, load, slew and global and local process parameters. Enhancing the conventional libraries to be voltage and temperature scal- able with similar accuracy requires on an average 4x more SPICE characterization runs.
Citation:
Bishnu Prasad Das, Janakiraman V. Bharadwaj Amrutur, H.S. Jamadagni, N.V. Arvind, "Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations," vlsid, pp.685-691, 21st International Conference on VLSI Design (VLSI Design 2008), 2008 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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