A 9 bit 400 MHz CMOS Double-Sampled Sample-and-Hold Amplifier

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Sounak Roy Articles by Swapna Banerjee

21st International Conference on VLSI Design (VLSI Design 2008)

Hyderabad, India

January 04-January 08

ISBN: 0-7695-3083-4

	ASCII Text	x
	Sounak Roy, Swapna Banerjee, "A 9 bit 400 MHz CMOS Double-Sampled Sample-and-Hold Amplifier," VLSI Design, International Conference on, pp. 323-329, 21st International Conference on VLSI Design (VLSI Design 2008), 2008.

	BibTex	x
	@article{ 10.1109/VLSI.2008.78, author = {Sounak Roy and Swapna Banerjee}, title = {A 9 bit 400 MHz CMOS Double-Sampled Sample-and-Hold Amplifier}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2008}, issn = {1063-9667}, pages = {323-329}, doi = {http://doi.ieeecomputersociety.org/10.1109/VLSI.2008.78}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - A 9 bit 400 MHz CMOS Double-Sampled Sample-and-Hold Amplifier SN - 1063-9667 SP323 EP329 A1 - Sounak Roy, A1 - Swapna Banerjee, PY - 2008 VL - 0 JA - VLSI Design, International Conference on ER -

Sounak Roy

Swapna Banerjee

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VLSI.2008.78

fier(SHA) is described here.The circuit is designed as a front end sampler of a low-power,high-speed analog to digital converter.The SHA uses double-sampling technique to achieve high speed with reasonably low power consumption.Using 0 .18? CMOS technology,a resolution of 9 bit has been achieved at a sampling rate of 400MHz.Also,to acquire superior linearity, boot-strapping technique has been used while implementing the switches and to reduce clock feed through, concept of bottom plate sampling has been utilized.Using a supply voltage of 1.8 V and a signal swing of 0 .6Vpp the circuit consumes approximately 10 mW of power.

Citation:

Sounak Roy, Swapna Banerjee, "A 9 bit 400 MHz CMOS Double-Sampled Sample-and-Hold Amplifier," vlsid, pp.323-329, 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.