Analysis of Delay Variation in Encoded On-Chip Bus Signaling under Process Variation

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21st International Conference on VLSI Design (VLSI Design 2008)

Hyderabad, India

January 04-January 08

ISBN: 0-7695-3083-4

	ASCII Text	x
	Sampo Tuuna, Jouni Isoaho, Hannu Tenhunen, "Analysis of Delay Variation in Encoded On-Chip Bus Signaling under Process Variation," VLSI Design, International Conference on, pp. 228-234, 21st International Conference on VLSI Design (VLSI Design 2008), 2008.

	BibTex	x
	@article{ 10.1109/VLSI.2008.73, author = {Sampo Tuuna and Jouni Isoaho and Hannu Tenhunen}, title = {Analysis of Delay Variation in Encoded On-Chip Bus Signaling under Process Variation}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2008}, issn = {1063-9667}, pages = {228-234}, doi = {http://doi.ieeecomputersociety.org/10.1109/VLSI.2008.73}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Analysis of Delay Variation in Encoded On-Chip Bus Signaling under Process Variation SN - 1063-9667 SP228 EP234 A1 - Sampo Tuuna, A1 - Jouni Isoaho, A1 - Hannu Tenhunen, PY - 2008 VL - 0 JA - VLSI Design, International Conference on ER -

Sampo Tuuna

Jouni Isoaho

Hannu Tenhunen

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VLSI.2008.73

In this paper, we model on-chip signaling over a bus con- sisting of encoding, drivers, transmission lines, receivers and decoding. We characterize the signaling circuitry as a function of its load capacitance. The effective load ca- pacitance seen by a driver is derived for the decoupling method and distributed RLC transmission line models. The driver delay and rise time corresponding to the derived ef- fective capacitance are used to derive the far-end voltage of a transmission line bus. The effects of process variation are taken into account in the characterization of the sig- naling circuitry and in the wire analysis. The overall delay variation of the bus due to device and wire process varia- tion is then calculated. The model is verified by comparing it to HSPICE. We implement regular voltage mode, level- encoded dual-rail and 1-of-4 signaling circuitry and apply the derived model to analyze them. The implementation and analysis are done in 45 nm technology.

Citation:

Sampo Tuuna, Jouni Isoaho, Hannu Tenhunen, "Analysis of Delay Variation in Encoded On-Chip Bus Signaling under Process Variation," vlsid, pp.228-234, 21st International Conference on VLSI Design (VLSI Design 2008), 2008

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