Architectures based on nanoscale molecular devices are at- tracting attention for replacing CMOS architectures at the end of the semiconductor roadmap. The two most promising nan- otechnologies, according to ITRS, are silicon nanowires and carbon nanotubes. Although they offer unmatched densities for building logic, interconnect and memory, they suffer from very defect-prone manufacturing processes. This is further ex- acerbated by testing complexities where it is nearly impossible to detect all defects in a large nanoscale chip. Furthermore, the small structures in nanoscale architectures are susceptible to transient faults which can produce arbitrary soft errors. As a result, fault tolerance is necessary to make nanoscale archi- tectures practical and realistic. We propose an architecture that can tolerate a large number of undetected manufacturing faults as well as a large rate of transient faults. Our archi- tecture is characterized by multiple levels of redundancy and majority voting to correct errors caused by such faults. A key aspect of the architecture is that it contains a judicious balance of both nanoscale and traditional CMOS components. A com- panion to the architecture is a compiler with heuristics tailored to quickly and compactly map logic onto partially defective components. Experimental results demonstrate the efficacy of the architecture.