Power Attack Resistant Efficient FPGA Architecture for Karatsuba Multiplier

V
VLSID
2008
21st International Conference on VLSI Design (VLSI Design 2008)
Abstract - Power Attack Resistant Efficient FPGA Architecture for Karatsuba Multiplier

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21st International Conference on VLSI Design (VLSI Design 2008)

Hyderabad, India

January 04-January 08

ISBN: 0-7695-3083-4

	ASCII Text	x
	Chester Rebeiro, Debdeep Mukhpodhyay, "Power Attack Resistant Efficient FPGA Architecture for Karatsuba Multiplier," VLSI Design, International Conference on, pp. 706-711, 21st International Conference on VLSI Design (VLSI Design 2008), 2008.

	BibTex	x
	@article{ 10.1109/VLSI.2008.65, author = {Chester Rebeiro and Debdeep Mukhpodhyay}, title = {Power Attack Resistant Efficient FPGA Architecture for Karatsuba Multiplier}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2008}, issn = {1063-9667}, pages = {706-711}, doi = {http://doi.ieeecomputersociety.org/10.1109/VLSI.2008.65}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Power Attack Resistant Efficient FPGA Architecture for Karatsuba Multiplier SN - 1063-9667 SP706 EP711 A1 - Chester Rebeiro, A1 - Debdeep Mukhpodhyay, PY - 2008 VL - 0 JA - VLSI Design, International Conference on ER -

Chester Rebeiro

Debdeep Mukhpodhyay

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VLSI.2008.65

The paper presents an architecture to implement Karat- suba Multiplier on an FPGA platform. Detailed analy- sis has been carried out on how existing algorithms utilize FPGA resources. Based on the observations the work devel- ops a hybrid technique which has a better area delay prod- uct compared to the known algorithms. The results have been practically demonstrated through a large number of experiments. Subsequently, the work develops a masking strategy to prevent power based side channel attacks on the multiplier. It has been found that the proposed masked Hy- brid Karatsuba multiplier is more compact compared to ex- isting designs.

Citation:

Chester Rebeiro, Debdeep Mukhpodhyay, "Power Attack Resistant Efficient FPGA Architecture for Karatsuba Multiplier," vlsid, pp.706-711, 21st International Conference on VLSI Design (VLSI Design 2008), 2008

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