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21st International Conference on VLSI Design (VLSI Design 2008)
A Low Voltage, Low Ripple, on Chip, Dual Switch-Capacitor Based Hybrid DC-DC Converter
Hyderabad, India
January 04-January 08
ISBN: 0-7695-3083-4
ASCII Text
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Kaushik Bhattacharyya, Pradip Mandal, "A Low Voltage, Low Ripple, on Chip, Dual Switch-Capacitor Based Hybrid DC-DC Converter," VLSI Design, International Conference on, pp. 661-666, 21st International Conference on VLSI Design (VLSI Design 2008), 2008.
 
 
BibTex
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@article{ 10.1109/VLSI.2008.59,
author = {Kaushik Bhattacharyya and Pradip Mandal},
title = {A Low Voltage, Low Ripple, on Chip, Dual Switch-Capacitor Based Hybrid DC-DC Converter},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2008},
issn = {1063-9667},
pages = {661-666},
doi = {http://doi.ieeecomputersociety.org/10.1109/VLSI.2008.59},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - VLSI Design, International Conference on
TI - A Low Voltage, Low Ripple, on Chip, Dual Switch-Capacitor Based Hybrid DC-DC Converter
SN - 1063-9667
SP661
EP666
A1 - Kaushik Bhattacharyya,
A1 - Pradip Mandal,
PY - 2008
VL - 0
JA - VLSI Design, International Conference on
ER -
 
Here we propose a low voltage low ripple dual switch- capacitor based hybrid DC-DC converter which is suitable for high dropout embedded regulation. In the proposed topology, along with a linear regulator two switching capacitors are used to store and recycle the charge for better power efficiency. The linear regulator is used to reduce the amount of output voltage ripple that comes from the switching capacitors. The output ripple noise is further reduced by introducing a synthesized counter ripple through the linear regulator. With this noise reduction technique, for an acceptable output ripple noise, the switching capacitors are reduced to a value which can be implemented on chip. The proposed converter circuit is designed in 0.18? process for 3.3V to 1.25V conversion. With two switching capacitors of 150pF each, for 10mA load current and 50pF load capacitor, peak-peak output voltage ripple is only 45 mV and the achieved power efficiency is 64%
Citation:
Kaushik Bhattacharyya, Pradip Mandal, "A Low Voltage, Low Ripple, on Chip, Dual Switch-Capacitor Based Hybrid DC-DC Converter," vlsid, pp.661-666, 21st International Conference on VLSI Design (VLSI Design 2008), 2008
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