As the technology scales, reduction in transistor size creates many opportunities for increased circuit capabilities in re- duced chip area. In modern wide-issue processors, perfor- mance of the processor is directly impacted by the time de- lay complexity of the dynamic scheduling logic. In this paper, we analyze the scaling of time delay of instruction select logic at the submicron technologies, and also present novel designs that provide a single selection tree for two similar functional units. The designs are based on a tree structure using arbiter cells of two and four inputs which can handle one or two func- tional units. The effects of technology and design decisions are shown based on simulations using four submicron tech- nologies. The delays in the select logic trees are shown to de- crease by an average of 60% from 130nm technology to 45nm technology when servicing a single functional unit. The dou- ble grant arbiter cells are shown to build a tree that will serve multiple functional units simultaneously with 65% lesser de- lay as compared to multiple single-grant trees1.