21st International Conference on VLSI Design (VLSI Design 2008) Throughput Efficient Parallel Implementation of SPIHT Algorithm Hyderabad, India January 04-January 08 ISBN: 0-7695-3083-4
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VLSI.2008.48
We present a throughput efficient FPGA implementation of the `Set Partitioning in Hierarchical Trees' (SPIHT) algorithm for compression of images. The SPIHT uses inherent redundancy among wavelet coefficients and suited for both gray and color images. The SPIHT algorithm uses dynamic data structures which hinders hardware realization. In our FPGA implementation we have modified basic SPIHT in two ways, one by using static (fixed) mappings which represent significant information and the other by interchanging the sorting and refinement passes. A hardware realization is done in a Xilinx XC2S30 device. Significant compression ratio and throughput is obtained for a sample image of size 128 x128 pixels
Citation:
Anilkumar V. Nandi, R.M. Banakar, "Throughput Efficient Parallel Implementation of SPIHT Algorithm," vlsid, pp.718-725, 21st International Conference on VLSI Design (VLSI Design 2008), 2008 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||