21st International Conference on VLSI Design (VLSI Design 2008) Energy Reduction in SRAM using Dynamic Voltage and Frequency Management Hyderabad, India January 04-January 08 ISBN: 0-7695-3083-4
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VLSI.2008.47
This paper describes a dynamic voltage frequency control scheme for a 256X64 SRAM block for reducing the energy in active mode and stand-by mode. The DVFM control system monitors the external clock and changes the supply voltage and the body bias so as to achieve a significant reduction in energy. The behavioral model of the proposed DVFM control system algorithm is described and simulated in HDL using delay and energy parameters obtained through SPICE simulation. The frequency range dictated by an external controller is 100MHz to 1GHz. The supply voltage of the complete memory system is varied in steps of 50mV over the range of 500mV to 1V. The threshold voltage range of operation is ?100mV around the nominal value, achieving 83.4% energy reduction in the active mode and 86.7% in the stand-by mode. This paper also proposes a energy replica that is used in the energy monitor subsystem of the DVFM system. Index Terms--Delay Monitor, DVFM, Energy reduction, Energy monitor, Pareto optimal curve, Replica circuits, SRAM.
Citation:
Mohammed Shareef I, Pradeep Nair, Bharadwaj Amrutur, "Energy Reduction in SRAM using Dynamic Voltage and Frequency Management," vlsid, pp.503-508, 21st International Conference on VLSI Design (VLSI Design 2008), 2008 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||